This invention relates generally to a re-programmable logic integrated circuit, such as a field programmable gate array (hereinafter referred to as FPGA), a programmable logic device (hereinafter referred to as PLD), which is integrated in a factory automation (FA) device, a communication device, a household electrical appliance, and so forth. Particularly, this invention relates to an art for constructing a CPU core on the logic integrated circuit.
As to a logic integrated circuit such as a conventional FPGA, PLD, wherein a user completes functions by themselves, in the case of constructing a complicated analytic logic, there has been adopted a method of directly describing analytic logic in a hardware description language, and creating a hardware circuit corresponding to said logic. Compared with this, in an ASIC (Application Specific IC) field, many kinds of circuits adopt a construction of a system LSI having a CPU core, and have adopted a processing method by using a program in the CPU for complicated analytic processing.
However, as to the FPGA or PLD wherein a hardware circuit corresponding to the above-mentioned conventional analytic logic is created, in the case of constructing the complicated analytic logic, the circuit increases its scale. Besides, in the case of constructing a circuit having a logic in which a protocol is frequently renewed, the hardware circuit has to be rearranged every time the logic is renewed. Further, in the case of directly integrating the CPU core employed in said conventional ASIC into the FPGA or PLD, a degree of using a gate increases, and an area of the CPU core on the FPGA or PLD also increases. Furthermore, since the CPU core used in the conventional ASIC is created without considering wiring delay characteristics inside the circuit, when integrated on the FPGA or PLD, the CPU core reduces its performance, and decreases its operational speed. Moreover, in the conventional CPU core, if a memory for storing programs or data on a three-stage pipeline construction is a complete synchronous memory, and when a load instruction from the memory to a register and a store instruction from the register to the memory are continuously carried out, a timing of reading out data from the memory to the register is late for a timing of writing in data from the register to memory, so that pipeline stall occurs, which causes a problem of decreasing processing speed.